In order to allow the read only memory (ROM) to be of a large scale structure, it is most suitable to adopt a cell structure of the NAND type in which the cell size is reduced by connecting in series transistors functioning as a memory cell. The principle of the operation of such a cell is schematically shown in FIGS. 1 and 2.
FIG. 1 shows the cell system of the NAND type mask ROM, and FIG. 2 shows a readout of this ROM. In these figures, reference numerals 11 denote bit lines, 22 word lines, 33 depletion type transistors, and 44 enhancement type transistors, respectively. In the case of reading data in the cell A in these figures, gates W.sub.1, W.sub.3 and W.sub.4 are caused to have a high voltage (e.g., 5 V), and the gate W.sub.2 is caused to have zero volts. In addition, the drain (bit line b.sub.1) is stepped up. At this time, if a current flows, the cell A is considered to be comprised of a depletion type transistor, and, on the other hand, if no current flows, the cell A is considered to be comprised of an enhancement type transistor. In this mask ROM, discrimination between "0" and "1" of data is made in dependency upon whether the transistor is of the depletion type or the enhancement type. In order to allow the transistor to be of depletion type, impurities of a conductivity type opposite to that of the substrate are ion-implanted into the portion below the electrode of the substrate. This ion implantation will be called ROM implantation hereinafter.
To miniaturize such a NAND type cell, it is sufficient to allow the pitches between transistors connected in series to be as small as possible. To reduce such pitches, two-layer polysilicon was conventionally employed as the gate electrode.
The process of the conventional example for preparing a device of such a structure is shown in FIGS. 3A to 3C.
As seen from FIG. 3A, e.g., a p-type silicon substrate or a p-type well within an n-type substrate may be used as the substrate 1. A gate oxide film 2 is formed on the substrate 1. Thereafter, a resist 3 is coated or covered over the region except for a region where a transistor desired to be of depletion type is to be formed. By using the resist 3 as a mask, impurity 4 of a conductivity type opposite to that of the substrate, e.g. phosphorus is ion-implanted into the region where an impurity layers 4A are to be formed, e.g., under the condition of an acceleration voltage of 40 KeV, and a dose quantity of 3.times.10.sup.13 cm.sup.-2 (ROM implantation).
As seen from FIG. 3B, a polysilicon layer 5A is then formed so that its thickness is equal to about 4000 .ANG.. This layer 5A is processed by the reactive ion etching (RIE) to form first gate electrodes 5.
Thereafter, as seen from FIG. 3C, an inter-gate-electrode insulating film 6 is formed by thermal oxidation at a temperature of 900.degree. C. Then, a polysilicon layer 7A having a thickness of 4000 .ANG. is formed. This layer 7A is processed by RIE to form second gate electrodes 7. At the time of forming the second gate electrodes 7, RIE processing is carried out so that the end portions of the second gate electrodes 7 overlap with the upper parts of the first gate electrodes 5.
Let now consider how the lower limit of the space S1 between first electrodes 5 is determined by the conventional process described above.
In FIG. 4, S1 represents a space between first electrodes 5, S2 a ROM implantation mask space, L.sub.min a line minimum value of the ROM implantation mask, Leff.sub.min a transistor minimum effective channel length, .DELTA.x an expansion of impurities implanted by the ROM implantation, and .DELTA.M an alignment margin. In FIG. 4, the respective values are assumed as follows.
The processing limit of lithography is assumed to be 0.7 .mu.m/0.7 .mu.m (line L.sub.min /space S.sub.min).
The alignment margin .DELTA.M of lithography is assumed to be 0.25 .mu.m in the case of direct alignment.
The expansion .DELTA.x in a lateral direction of ROM implanted impurities is assumed to be 0.15 .mu.m.
The minimum effective channel length (Leff.sub.min) of the transistor comprised of the second gate electrode 7 is assumed to be 0.4 .mu.m.
In the ROM implantation and formation of the first gate electrodes 5, positioning of lithography is carried out indirectly, e.g., through a field oxide film. For this reason, the alignment shift margin .DELTA.M is equal to .sqroot.2.times.0.25.div.0.35 .mu.m.
In the case where ROM implantation is carried out into the portion below the space between the first gate electrodes 5 arranged in a row, the space S1 between first gate electrodes 5 is represented by the following relationship with respect to the lower limit of the minimum effective channel of the transistor constituted with second gate electrode 7 therebetween:
The width of the space between first gate electrodes 5.gtoreq.Leff.sub.min +2.DELTA.x+2.DELTA.M.div.1.4 (.mu.m)=S1.
Further, the above-mentioned space width is represented by the following relationship also with respect to the minimum value L.sub.min of the line width of the implantation mask for carrying out the ROM implantation:
The width of the space between first gate electrodes 5.ltoreq.L.sub.min +2.DELTA.M.div.1.4 (.mu.m)=S1.
From either point of view, S1 is nearly equal to 1.4 .mu.m. Thus, it is seen that the space width between first gate electrodes 5 is twice as large than the limit S.sub.min =0.7 (.mu.m) in processing of the space between first gate electrodes 5, and therefore the alignment shift margin of the ROM implantation gives a great obstacle to miniaturization of cell.
In this prior art, calculation similar to the above is carried out in the case of carrying out ROM implantation into the portion below the space between the second gate electrodes adjacent to each other. For this reason, the lower limit of the line width of the first gate electrode becomes equal to a value of 1.4 .mu.m or more.
Thus, the size in a direction where transistors are connected in series per cell becomes equal to (1.4+1.4)/2=1.4 .mu.m.
A conventional process partially improved in connection with the alignment shift is shown in FIGS. 5A to 5D.
As seen from FIG. 5A, in order to form an impurity regions 4A below the regions where first gate electrodes 5 are to be formed, a first ROM implantation of the impurity 4 is initially carried out by using resist 3 as a mask.
As seen from FIG. 5B, first gate electrodes 5 are then formed.
As seen from FIG. 5C, an inter-gate-electrode insulating film 6 is then formed. Thereafter, in order to form impurity regions 9A below the regions where second gate electrodes 7 are to be formed by using resist 8 as a mask, a second ROM implantation of an impurity 9 is executed. As the impurity 9 of a conductivity type opposite to that of the substrate 1 at this time, phosphorus .sup.31 p.sup.+ is implanted into, e.g., a p-type substrate under the condition of a dose quantity of the order of 10.sup.13 cm.sup.-2 at 40 KeV. The ion 9 range at this time is smaller than 4000 .ANG. of the first gate electrode thickness. For this reason, ions 9 do not come into the portions below the first gate electrodes 5. Thus, impurities are implanted into the channel portions below the second gate electrodes 7 by self-alignment. Accordingly, the restriction expressed as the first gate electrode line width .gtoreq.1.4 .mu.m as in the prior art of FIGS. 3A to 3C is eliminated. However, the restriction of the width of the space S1 between first gate electrodes 5 is not eliminated, so this width becomes equal to a value of 1.4 (.mu.m) or more.
In implementing miniaturization to a semiconductor memory, such as, for example, a NAND type mask ROM of two-layer electrodes 5, 7 structure in a manner stated above, the alignment shift margin of ion-implanted impurities constitutes a great obstacle as described above.